Memory
NOTE: Memory configurations listed do not apply to "Factory Integrated Models".
Memory Subsystem Architecture
Each processor contains two Memory Controllers as shown in the Processor/Memory interconnect figure below. Each Memory controller has two Scalable Memory Interface (SMI) buses operating in lockstep where each SMI bus connects to a memory buffer. The purpose of the buffer is to convert SMI to DDR3. Each buffer has two DDR3 channels and can support up to four DIMMs for a total of eight DIMMs per cartridge.
Memory speed is not affected by number of DIMMs or ranks. All DIMMs will run at the highest possible speed for a given processor.
DDR3 memory speed is a function of the processors QPI bus speed such that
Processors with a QPI speed of 6.4GT will run memory at 1066MHz
Processors with a QPI speed of 5.6GT will run memory at 978MHz
Processors with a QPI speed of 4.8GT will run memory at 800 MHz